Marcelo Orenes-Vera
Currently working on next-generation GPU clusters to drive AI innovation.
Research Interests
- Deep Learning Computer Architecture, Parallel Computing & HPC
- Chiplet-based Systems, Domain-specific Architectures & Software-Hardware Co-design
- Data-centric Computing for Memory-intensive Applications
- Agile & AI-assisted Hardware Design & Verification
- Formal Verification & Security
Education
Princeton University, NJ
Adviser: Prof. Margaret Martonosi and Prof. David Wentzlaff
Dissertation: Navigating Heterogeneity and Scalability in Modern Chip Design
Princeton University, NJ
University of Murcia, Spain
Thesis: An Indoor Location and Guidance System with Automated User Trajectory Analysis.
University of Hasselt, Belgium
Refereed Conference Publications
Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems.
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi In The International Symposium on Performance Analysis of Systems and Software (ISPASS), 2024. PDF | Code
Using LLMs to Facilitate Formal Verification of RTL.
Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff. PDF | Code
AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware.
Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Luca Benini, Gernot Heiser, David Wentzlaff, Margaret Martonosi In the 56th International Symposium on Microarchitecture (MICRO). IEEE/ACM 2023. PDF | Code
Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees.
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff. PDF | Code
DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications.
Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff. PDF | Code
Wafer-Scale Fast Fourier Transforms.
Marcelo Orenes-Vera, Ilya Sharapov, Robert Schreiber, Mathias Jacquelin, Philippe Vandermersch, Sharan Chetlur. In the 37th International Conference in Supercomputing (ICS ‘23). PDF
Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications.
Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi. In the 29th IEEE Symposium on High-Performance Computer Architecture (HPCA ‘23). PDF
Cohort: Software-Oriented Acceleration for Heterogeneous SoCs.
Tianrui Wei, Nazerke Turteyeva, Marcelo Orenes-Vera, Omkar Lonkar, Jonathan Balkind. In Proc. of the 28th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), ACM 2023. PDF | Code
DECADES: A 67mm², 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.
Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, et al. In Proc. of the Custom Integrated Circuits Conference (CICC), IEEE 2023. PDF
CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm², 1.92 MOPS/LUT, Fully Synthesizable, Cache-Coherent, Embedded FPGA.
Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, et al. In Proc. of the Custom Integrated Circuits Conference (CICC), IEEE 2023. PDF
Tiny but Mighty: Designing and Realizing Scalable Latency Tolerance for Manycore SoCs
Marcelo Orenes-Vera, Aninda Manocha, Jonathan Balkind, Fei Gao, Juan L. Aragón, David Wentzlaff, Margaret Martonosi In the 49th Annual International Symposium on Computer Architecture (ISCA ‘22)
IEEE MICRO Top Picks honorable mention. PDF | Code | Presentation
AutoSVA: Democratizing Formal Verification of RTL Module Interactions
Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi In the 58th ACM/IEEE Design Automation Conference (DAC 21). PDF | Code
MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems
Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi In The International Symposium on Performance Analysis of Systems and Software (ISPASS), 2020
Nominated for Best Paper Award. PDF | Code
A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation
Tyler Sorensen, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi. In International Conference on Computer Aided Design (ICCAD), ACM/IEEE 2020. PDF
Journal Publications
CIFER: A Cache-Coherent 12nm 16mm² SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm² Synthesizable eFPGA.
Ang Li, Ting-Jung Chang, Fei Gao, Marcelo Orenes-Vera, et al. In Solid-State Circuit Letters. IEEE 2023. PDF
RECITE: A Framework for User Trajectory Analysis in Cultural Sites.
Marcelo Orenes-Vera, Fernando Terroso, Mercedes Valdes-Vela. In Journal of Ambient Intelligence (JAISE), 2021. PDF | Code